علوم رایانش و فناوری اطلاعات

مدیریت اوج توان در سیستم‌های رزرو-آماده‌باش

نویسندگان

دانشکده ی مهندسی کامپیوتر، دانشگاه صنعتی شریف، تهران، ایران

چکیده

سیستم ­های­ بی­درنگ عمدتاً باید دارای قابلیت اطمینان بالا باشند. افزایش تعداد هسته‌های پردازشی در یک تراشه امکان استفاده از روش‌های تحمل‌پذیری اشکال مبتنی بر افزونگی سخت‌افزاری را برای این سیستم‌ها فراهم می‌کند؛ اما این روش‌ها ممکن است باعث افزایش مصرف توان و عبور اوج توان مصرفی از توان حرارتی طراحی (TDP) شوند. توان حرارتی طراحی آن حد از دما است که واحد خنک­ کننده­ می‌تواند برای آن جوابگو باشد. در صورت عبور دما از این حد، سیستم (بدون کنترل طراح سیستم) راه ­اندازی مجدد می‌شود یا کارایی خود را به شدت کاهش می‌دهد تا از آسیب دائمی جلوگیری گردد. از این ­رو، مطالعه‌ی تأثیر روش‌های تحمل‌پذیری اشکال بر اوج توان مصرفی و ارائه‌ی روش‌هایی برای دست­یابی به تحمل‌پذیری اشکال در سیستم‌های بی‌درنگ تحت محدودیت‌ توان حرارتی طراحی حائز اهمیت است. در این پژوهش، یک روش مدیریت اوج توان مصرفیِ آگاه به قابلیت اطمینان برای سیستم­ های  چندهسته ­ای بی­درنگ که از افزونگی­ سخت­ افزاری رزرو-آماده­ باش استفاده می­ کنند، ارائه می ­شود.

کلیدواژه‌ها

  • [1] L. Benini, A. Bogliolo, and G. De Micheli, “A Survey of Design Techniques for System-Level Dynamic Power Management,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 8, pp. 299 – 316, 2000.
  • [2] D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,” in Proc. 27th annual Int’l symp. Computer architecture (ISCA), pp. 83-94, 2000.
  • [3] T. Chantem, X. Hu, and R. Dick, “Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 19, no. 10, pp. 1884-1897, 2011.
  • [4] J.-J. Chen, S. Wang, and L. Thiele, “Proactive Speed Scheduling for Real-Time Tasks under Thermal Constraints,” in Proc. IEEE 15th Real-Time Technology and Applications Symp. (RTAS), pp. 141-150, 2009.
  • [5] R. I. Davis and A. Burns, “A Survey of Hard Real-Time Scheduling for Multiprocessor Systems,” ACM Computing Surveys (CSUR), Vol. 43, no. 4, pp.1-44, 2011.
  • [6] A. Ejlali, B. M. Al-Hashimi, and P. Eles, “A Standby-Sparing Technique with Low Energy-Overhead for Fault-Tolerant Hard Real-Time Systems,” in Proc. IEEE/ACM 7th Int’l conf. Hardware/software codesign and system synthesis (CODES+ISSS), pp. 193-202, 2009.
  • [7] X. Wu and Z. Yan, “CAC Codec Designs Based On Numeral Systems,” in IEEE Workshop on Signal Processing Systems, 2009.
  • [8] X. Wu and Z. Yan, “Efficient CODEC Designs for Crosstalk Avoidance Codes Based on Numeral Systems,” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 548-558, 2011.
  • [9] S. R. Sridhara, A. Ahmed, and N. R. Shanbhag, “Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses,” in Computer Design: VLSI in Computers and Processors, pp. 12-17, 2004.
  • [10] W.-W. Hsieh, P.-Y. Chen, and C.-Y. Wang, “A Bus-Encoding Scheme for Crosstalk Elimination,” in IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, vol. 26, no. 12, pp. 2222-2227, 2007.
  • [11] K. Ramesh and E. Srinivas, “FPGA Implementation of Codec Design for Optimal,” in International Journal of Science and Research (IJSR), vol. 2, no. 2, pp. 614-622, 2013.
  • [12] C. Duan, K. Gulatit, and S. P. Khatrit, “memory-based Cross-talk Canceling CODECs for On-chip Buses,” in Proceeding of IEEE International Symposium on Circuits and Systems, 2006.
  • [13] C. Duan, C. Zhu, and S. P. Khatri, “Forbidden Transition Free Crosstalk,” in ACM/IEEE Design Automation Conference, 2008.
  • [14] M.A. Haque, H. Aydin, and D. Zhu, “Energy Management of Standby-Sparing Systems for Fixed-Priority Real-Time Workloads,” in Proc. Int‘l Green Computing Conf. (IGCC), pp. 1-10, 2013.
  • [15] N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki, Toward Dark Silicon in Servers, Micro-44, 2011.
  • [16] W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. T. Kandemir, and M. J. Irwin, “Thermal-Aware Task Allocation and Scheduling for Embedded Systems,” in Proc. ACM/IEEE Conf. Design, Automation, and Test in Europe (DATE), vol. 2, pp. 898-899, 2005.
  • [17] Intel Corporation, “Desktop 3rd Generation Intel Core Processor Family Thermal Mechanical Specifications and Design Guidelines,” 2013.
  • [18] C. Isci and M. Martonosi, “Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data,” in Proc. IEEE/ACM 36th Int’l Symp. Microarchitecture (MICRO), pp. 93-104, 2003.
  • [19] V. Izosimov, I. Polian, P. Pop, P. Eles, and Z. Peng, “Analysis and Optimization of Fault-tolerant Embedded Systems with Hardened Processors,” in Proc. Design, Automation and Test in Europe Conf. and Exhibition (DATE), pp. 682-687, 2009.
  • [20] R. Jejurikar, C. Pereira, and R. Gupta, “Leakage Aware Dynamic Voltage Scaling for Real-Time Embedded Systems,” in Proc. IEEE 41st annual Design Automation Conf. (DAC), pp. 275-280, 2004.
  • [21] B. Johnson, Design, and Analysis of Fault-Tolerant Digital Systems, Reading, Mass.: Addison-Wesley Pub. Co., 1989.
  • [22] S. Kodase, S. Wang, Z. Gu, and K.G. Shin, “Improving Scalability of Task Allocation and Scheduling in Large Distributed Real-Time Systems Using Shared Buffers,” in Proc. IEEE 9th Real-Time Technology and Applications Symp. (RTAS), pp. 181-188, 2003.
  • [23] V. Kontorinis, A. Shayan, R. Kumar, and D. Tullsen, “Reducing Peak Power with a Table-Driven Adaptive Processor Core,” in Proc. 42nd Ann. IEEE/ACM Int’l Symp. Microarchitecture (MICRO), pp. 189-200, 2009.
  • [24] H. Kopetz, Real-Time Systems: Design Principles for Distributed Embedded Applications, KLUWER Academic Publishers, 2002.
  • [25] I. Koren, and C.M. Krishna, Fault-Tolerant Systems, Morgan Kaufmann, Elsevier, San Francisco, CA, 2007.
  • [26] J. Lee, B. Yun, and K. Shin, “Reducing Peak Power Consumption in Multi-Core Systems without Violating Real-Time Constraints,” IEEE Trans. Parall. Distr. Syst., vol. 25, No. 4, pp. 1024 – 1033, 2014.
  • [27] B. Lee, J. Kim, Y. Jeung, and J. Chong, “Peak Power Reduction Methodology for Multi-Core Systems,” in Int’l SoC Design Conf. (ISOCC), pp.233-235, 2010.
  • [28] P. Marwedel, Embedded System Design. Dortmund (Germany): Springer, 2006.
  • [29] K. Meng, R. Joseph, R.P. Dick, and L. Shang, “Multi-Optimization Power Management for Chip Multiprocessors,” in Proc. 17th Int’l Conf. Parallel Architectures and Compilation Techniques (PACT), pp. 177-186, 2008.
  • [30] R. McGowen, C. Poirier, C. Bostak, J. Ignowski, M. Millican, W. Parks, and S. Naffziger, “Power and Temperature Control on a 90-nm Itanium Family Processor,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 229-237, Jan. 2006.
  • [31] M. Mohaqeqi, M. Kargahi, and A. Movaghar, “Analytical Leakage-Aware Thermal Modeling of a Real-Time System,” IEEE Trans. Computers, vol. 63, no. 6, pp. 1378-1392, 2014.
  • [32] P. Pillai, and K.G. Shin, “Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems,” in Proc. 18th ACM Symp. Operating Systems Principles (SOSP), pp. 89-102, 2001.
  • [33] S. Polena, Fault-Tolerant Real-Time Systems: The Problem of Replica Determinism, KLUWER Academic Publishers, 1996.
  • [34] P. Pop, V. Izosimov, P. Eles, and Z. Peng, “Design Optimization of Time and Cost-Constrained Fault-Tolerant Embedded Systems with Checkpointing and Replication,” IEEE Trans. Very Large Integrated (VLSI) Systems, vol. 17, pp. 389-402, 2009.
  • [35] F. R. Poursafaei, S. Safari, M. Ansari, M. Salehi, and A. Ejlali, “Offline Replication and Online Energy Management for Hard Real-Time Multicore Systems,” in Proc. 1th Int’l CSI Symp. Real-Time and Embedded Systems and Technologies (RTEST), pp. 1-7, 2015.
  • [36] D. Pradhan, Fault Tolerant Computer System Design, Prentice Hall, 1996.
  • [37] S. Rusu, S. Tam, H. Muljono, D. Ayers, and J. Chang, “A Dual- Core Multi-Threaded Xeon Processor with 16MB L3 Cache,” in Proc. IEEE Int’l Solid State Circuits Conf. (ISSCC), pp. 315-324, 2006.
  • [38] M.Salehi and A. Ejlali, “A Hardware Platform for Evaluating Low-Energy Multiprocessor Embedded Systems Based on COTS Devices,” IEEE Trans. Industrial Electronics, vol. 62, no. 3, pp. 1262-1269, 2015.
  • [39] M. Salehi, A. Ejlali, and B.M. Al-Hashimi, “Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems,” IEEE Trans. Parallel and Distributed Systems (TPDS), no. 99, 2015.
  • [40] M. Shafique, S. Garg, J. Henkel, and D. Marculescu, “The EDA Challenges in the Dark Silicon Era,” in Proc. IEEE 51st Int’l Design Automation Conf. (DAC), pp. 1-6, 2014.
  • [41] S. Wang, J.-J. Chen, Z. Shi, and L. Thiele, “Energy-Efficient Speed Scheduling for Real-Time Tasks under Thermal Constraints,” in Proc. IEEE 15th Int’l Conf. Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 201-209, 2009.
  • [42] B. Yun, K. Shin, and S. Wang, “Thermal-Aware Scheduling of Critical Applications Using Job Migration and Power-Gating on Multi-core Chips,” in Proc. 10th Int’l Conf. Trust, Security and Privacy in Computing and Communications (TSPCC), pp. 1083-1090, 2011.
  • [43] J. Zhuo and C. Chakrabarti, “System-Level Energy-Efficient Dynamic Task Scheduling,” in Proc. 42nd Design Automation Conf. (DAC), pp. 628-631, 2005.
  • [44] D. Zhu and H. Aydin, “Reliability-Aware Energy Management for Periodic Real-Time Tasks,” IEEE Trans. Computers, vol. 58, no. 10, pp. 1382 – 1397, 2009.
  • [45] W. Munawar, H. Khdr, S. Pagani, M. Shafique, J.-J. Chen, and J. Henkel, “Peak Power Management for Scheduling Real-Time Tasks on Heterogeneous Many-Core Systems,” in IEEE 20th Int’l Conf. Parallel and Distributed Systems (ICPADS), pp. 208-209, 2014.
  • [46] M. Khavari Tavana, M. Salehi, and A. Ejlali, “Feedback-Based Energy Management in a Standby-Sparing Scheme for Hard Real-Time Systems,” in Proc. IEEE Real-Time Systems Symp. (RTSS), pp. 349-356, 2011.
  • [47] Y. Guo, D. Zhu, and H. Aydin, “Reliability-Aware Power Management for Parallel Real-Time Applications with Precedence Constraints,” in Proc. Int’l Green Computing Conf. and Workshops (IGCC), pp.1-8, 2011.
  • [48] X. Qi, D. Zhu, and H. Aydin, “Global Scheduling Based Reliability-Aware Power Management for Multiprocessor Real-Time Systems,” J. Real-Time Syst., vol. 47, no. 2, pp. 109-142, 2011.
  • [49] S. Pagani, H. Khdr, J. Chen, M. Shafique, M. Li and J. Henkel, “Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manycore Systems in Dark Silicon,” IEEE Transactions on Computers, vol. 66, no. 1, pp. 147-162, 1 Jan. 2017.
  • [50] M. Ansari, S. Safari, A. Y. Khaksar, M. Salehi, and A. Ejlali, “Peak Power Management to Meet Thermal Design Power in Fault-Tolerant Embedded Systems,” IEEE Trans. on Par. and Dis. Sys., vol. 30, no. 1, 2019.
  • [51] H. Khdr, S. Pagani, E. Sousa, V. Lari, A. Pathania, F.Hanning, M. Shafique, J. Teich, and J. Henkel “Power Density-Aware Resource Management for Heterogeneous Tiled Multicores,” in IEEE Transactions on Computers, vol. 66, no. 3, pp. 488-501, 2017.
  • [52] S. Safari, M. Ansari, G. Ershadi and S. Hessabi, "On the Scheduling of Energy-Aware Fault-Tolerant Mixed-Criticality Multicore Systems with Service Guarantee Exploration," IEEE Transactions on Parallel and Distributed Systems, 2019.
  • [53] M. Shafique, S. Garg, “Computing in the Dark Silicon Era: Current Trends and Research Challenges,” IEEE Design & Test (DnT), vol. 34, no. 2, pp. 5-7, 2017.
علوم رایانش و فناوری اطلاعات
دوره 17، شماره 1
بهار و تابستان
اردیبهشت 1398